SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Japanese Patent JP2012054453

A

To provide a semiconductor device manufacturing method that can form fine wiring at a high aspect ratio in high density.

The semiconductor device manufacturing method comprises steps of forming a first wiring trench and a second wiring trench next to each other on an interlayer insulator, providing first wiring in the first wiring trench with a space above and second wiring in the second wiring trench with a space above, performing isotropic etching to form a first mask trench which is formed by expanding a width of the first wiring trench and a second mask trench which is formed by expanding a width of the second wiring trench, filling the first mask trench and the second mask trench with a mask insulation material to form a first mask insulator in the first mask trench and a second mask insulator in the second mask trench, performing anisotropic etching by use of the first mask insulator and the second mask insulator as a mask to form a hole passing between the first wiring and the second wiring and penetrating the interlayer insulator in a self-aligning manner with respect to the first mask insulator and the second mask insulator, and filling the hole with a conductive material to form a plug.

HIROTA TOSHIYUKI

JP2010196690A

March 15, 2012

September 02, 2010

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ELPIDA MEMORY INC

H01L21/8242; H01L27/10; H01L27/105; H01L27/108; H01L45/00; H01L49/00

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Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata

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