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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6395658
Kind Code:
A
Abstract:

PURPOSE: To increase the density of integration by isolating an element constituting at least a memory cell formed onto a compound semiconductor GaAs substrate by a P-N junction while shaping the element onto a P-type conductive layer.

CONSTITUTION: A memory cell is organized of depletion type Schottky gate type field effect TRs 1, 2 for load, enhancement type Schottky gate type field effect TRs 3, 4 for drive and enhancement type Schottky gate type field effect TRs 5, 6 having transfer gates. These six TRs are shaped onto a P-type conductive layer 14 as shown in the figure, and brought to the same potential as the lowest potential of a circuit and employed. Numeric 7 represents a semi- insulating GaAs substrate, 8, 9 high concentration N-type regions, 10 an N-type active layer, 11, 12 ohmic electrodes for a source and a drain, 13 a gate electrode and 14 the P-type conductive layer in the figure.


Inventors:
UENOYAMA TAKESHI
YAKIDA HIDEKI
Application Number:
JP24247486A
Publication Date:
April 26, 1988
Filing Date:
October 13, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L27/10; H01L21/338; H01L21/76; H01L27/06; H01L29/812; (IPC1-7): H01L21/76; H01L27/10; H01L29/80
Attorney, Agent or Firm:
Toshio Nakao



 
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