Title:
通信用半導体集積回路
Document Type and Number:
Japanese Patent JP4647461
Kind Code:
B2
Abstract:
The communication semiconductor integrated circuit includes serial-signal processing circuits having low-pass filters and variable gain amplifier circuits cascade-connected in series. The low-pass filters constituting the serial-signal processing circuit each include a variable capacitance circuit composed of capacitance elements and switching elements connected in series to the capacitance elements, respectively, and capable of selecting the capacitance elements to change capacitance of the low-pass filter. A reference clock signal is supplied to the circuit containing the low-pass filters upon turning on of a power supply, for example, to determine a deviation of a delay time in the circuit to a design value and on and off states of the switching elements of the variable capacitance circuit are set so that the deviation of the delay time is minimized.
Inventors:
Uchitomi Ken
Takao Okazaki
Senda Sakae
Yasuo Shima
Gary Smith
Takao Okazaki
Senda Sakae
Yasuo Shima
Gary Smith
Application Number:
JP2005310586A
Publication Date:
March 09, 2011
Filing Date:
October 26, 2005
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H04B1/30; H03H1/02; H03H11/04; H03H11/12; H04L27/38
Domestic Patent References:
| JP2005020119A | ||||
| JP2002280839A |
Attorney, Agent or Firm:
Shizuyo Tamamura