To provide a semiconductor integrated circuit device, its testing device and testing method which enable scanning test without being affected by clock skew existing between clock domains, while restraining increase of circuit area and increase of test time duration of the semiconductor integrated circuit device.
In the semiconductor integrated circuit device, a selector is installed wherein output signals of two flip-flops having equal characteristic which are selected from adjacent two clock domains are inputted and either one of them is outputted according to a select signal. Output signal of one flip-flop and output signal of the other flip-flop are outputted one by one. Their output delay difference and phase difference for canceling the output delay difference are obtained. Clocks which gave the phase difference are supplied respectively to a plurality of the clock domains with which the semiconductor integrated circuit device is equipped.
Nobuyuki Kaneda
Katsuhiro Ito
Ishibashi Masayuki