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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH01260847
Kind Code:
A
Abstract:

PURPOSE: To ensure stable operation without effects on a TTL gate and other circuits on a semiconductor integrated circuit even if the potential of a ground is fluctuated, by isolating the ground of the totem pole output part of the TTL gate and the ground for an input part and a phase inverting part.

CONSTITUTION: The emitter of a transistor 16 and resistors 13 and 14 are connected to a ground 7. The emitter of a transistor 20 and a resistor 15 arc connected to a ground 8. A grounding pad 22 including the ground 7 and a grounding pad 8a including the ground 8 are isolated. The ground 7 for an input part 1 and a phase inverting part 2 and the ground 8 for a totem pole output part 3 are divided into the ground pad 22 and the ground pad 8a. Therefore, even if a through current flows in the totem pole output 3 and the level of the ground 8 is fluctuated, the ground 7 for the input part 1 and the phase inverting part 2 is not fluctuated. Therefore, the operation of a TTL gate does not become unstable.


Inventors:
IRIE HIROFUMI
Application Number:
JP8992188A
Publication Date:
October 18, 1989
Filing Date:
April 11, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/04; H01L21/822; H01L21/8222; H01L27/08; H01L27/082; H03F3/34; H03F3/347; H03F3/42; (IPC1-7): H01L27/04; H01L27/08; H03F3/347; H03F3/42
Domestic Patent References:
JPS5828852A1983-02-19
JPS61264747A1986-11-22
JPS60185291A1985-09-20
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)