To reduce a size of a power switch cell or a power switch area without falling a current driving capability.

In this semiconductor integrated circuit, at least one of a supply voltage supply line and a reference voltage supply line comprises a sub-wiring V-VDD or V-VSS in a circuit cell and a main wiring VSS or VSS arranged in a one direction. A gate electrode 20 of switching transistors SWP, SWN for controlling a connection and a non-connection between the sub-wiring and the main wiring is almost juxtaposed to a cell arranging direction (for instance, a row direction) of a circuit cell group which is supplied with power from the same main wirings VDD, VSS.