Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3278080
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor integrated circuit in which data matching is implemented at a high speed through the use of a simple circuit.
CONSTITUTION: The semiconductor integrated circuit having at least one 1st input terminal 117 and at least one 2nd input terminal 115 receiving a voltage signal, and at least one output terminal 113 to provide a predetermined signal at the output terminal 113 when a difference of numerals expressed by two sets of signals inputted respectively to the 1st and 2nd input terminals 117, 115 is smaller than a predetermined value includes at least two inverters 124, 125 comprising neuron MOS transistors(TRs) 101, 103 and is characterized in that the two sets of signals or signals subject to predetermined processing partly are inputted to at least one of input gates of each inverter.
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Inventors:
Naoshi Shibata
Koji Kotani
Tadahiro Ohmi
Koji Kotani
Tadahiro Ohmi
Application Number:
JP5774893A
Publication Date:
April 30, 2002
Filing Date:
February 22, 1993
Export Citation:
Assignee:
Naoshi Shibata
Tadahiro Ohmi
UCT Co., Ltd.
I&F Co., Ltd.
Tadahiro Ohmi
UCT Co., Ltd.
I&F Co., Ltd.
International Classes:
G06F7/04; G06G7/60; G06N3/063; H03K19/21; (IPC1-7): H03K19/21; G06F7/04; G06G7/60
Domestic Patent References:
| JP653431A | ||||
| JP677426A | ||||
| JP6139380A | ||||
| JP6244375A |
Attorney, Agent or Firm:
Hisao Fukumori
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