Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH1198008
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To keep logical amplitude constant and to perform a frequency dividing operation in entire high and low current areas by suppressing the reduction of logical amplitude caused accompanying the drop of control current with limit amplifiers which cascade plural flip-flop circuits. SOLUTION: A limiter amplifier circuit 3 of a preceding stage that consists of bipolar transistors Tr10 and Tr11 is connected to output terminals (q) and (/q) of a master stage A, and also, a limiter amplifier circuit 3 of a subsequent stage B that consists of bipolar transistors Tr24 and Tr22 is connected to output terminals Q and /Q of a slave stage B. Then, collectors of the transistors Tr10 and Tr11 of the circuit 3 feedbacks a signal to bipolar transistors Tr2 and Tr3, and Tr12 and Tr15, the logical amplitude of an F/F circuit of an initial stage is kept constant regardless of control current of the stages A and B, and the operations of switching transistors Tr1 to Tr14 and Tr12 to Tr15 are guaranteed.
Inventors:
ISHII NORIKO
Application Number:
JP25517297A
Publication Date:
April 09, 1999
Filing Date:
September 19, 1997
Export Citation:
Assignee:
NEC CORP
International Classes:
H03K21/00; H03K23/00; (IPC1-7): H03K23/00; H03K21/00
Attorney, Agent or Firm:
Sugano Naka