PURPOSE: To limit a pulse width of an input, and to prevent a malfunction caused by an influence of a noise, etc., by using an oscillating circuit, a counter, a comparator and a memory, for an inputting circuit.

CONSTITUTION: An oscillating circuit is constituted of a feedback circuit which has allowed outputs of 2 NORs 4 (or 2 NANDs) provided as logic circuits for inputting an input signal (a) from an input terminal 1, to pass through multistage inverters 2, 3 constituted of even stages of a delaying circuit, and has inputted the last stage outputs of these multistage inverters 2, 3 to the other of the 2 NORs, and also, a counter part 5, a comparator part 6, and a memory part 7 are provided. The counter part 5 inputs a clear signal for clearing a count from a terminal 10, brings output signals of 2 NORs (or 2 NANDs) of the feedback circuit to a count clock input. In this state, by controlling an active period of the input signal by the oscillating circuit containing the feedback circuit of 2 NORs 4, the counter 5, the comparator 6, and the memory 7, a malfunction caused by an influence of a noise, etc., is eliminated, and the active period of the input signal can be controlled from the inside.