SEMICONDUCTOR MEMORY DEVICE WITH ERROR DETECTION/ CORRECTION CIRCUIT

Title:

SEMICONDUCTOR MEMORY DEVICE WITH ERROR DETECTION/ CORRECTION CIRCUIT

Document Type and Number:

Japanese Patent JPS63129600

Kind Code:

A

Abstract:

PURPOSE: To check the normal operation of an ECC circuit at a stage of the function check of a chip by adding a ROM for an error detection/correction ECC checking.

CONSTITUTION: In initialization, checking data that cannot be produced from input data to which one bit out of 12 bits is destructed is written in the error checking code ROM 1, whereby the actions of an error detection circuit 8 and an error correction circuit 9 are checked. If the ROM 1 is selected through selection lines Xc and Yc when the ECC circuit normally operates, the circuits 8 and 9 are activated. As a result expective value is obtained from the output of the circuit 9. If the ECC circuit is not operating normally, data except for an expectation is obtained from the output of the circuit 9.

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Inventors:

HASHIMOTO KIYOKAZU

Application Number:

JP27712686A

Publication Date:

June 01, 1988

Filing Date:

November 19, 1986

Export Citation:

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Assignee:

NEC CORP

International Classes:

G06F11/10; G06F11/267; G06F12/16; G11C29/00; G11C29/02; G11C29/36; G11C29/42; (IPC1-7): G06F12/16; G11C29/00

Domestic Patent References:

JPS60136998A	1985-07-20
JPS59206951A	1984-11-22

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

Previous Patent: JPS63129599

Next Patent: JPS63129601