Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH10125066
Kind Code:
A
Abstract:

To filter out a noise and control influence of noise on an external circuit by providing a noise filter circuit in an output circuit to filter out the noise which propagates to an external circuit through a wiring.

When a potential of a contact Y is reduced, a PMOS transistor 202 in a noise filter circuit 20 turns on to connect the potential of contact Y to the power source voltage VEXT. Therefore, potential of the contact Y is increased up to VEXT and change of the potential of contact Y by a noise can be removed. Next, potential of the contact X also rises owing to the influence of the noise. However, an NMOS transistor 204 in the noise reduction circuit 20 turns on and the contact Y is connected to the power source voltage VEXT. Thereby, change of potential of the contact Y due to noise can be removed as explained above.


Inventors:
YOSHIMATSU TAKANORI
SAITO KAZUNARI
Application Number:
JP27069496A
Publication Date:
May 15, 1998
Filing Date:
October 14, 1996
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA CORP
International Classes:
G11C11/413; G11C11/409; H03K5/1252; (IPC1-7): G11C11/409; G11C11/413; H03K5/1252
Attorney, Agent or Firm:
Togawa Hideaki