PURPOSE: To improve integration by means of vertically supplying a substrate with an electric charge by a method wherein, in a memory utilizing a memory cell comprising a single transistor and a single capacitor as minimum unit, a channel region pierced by a word line is provided on the part where the word line and a bit line intersect while one end and the other end are respectively abutted against an electric charge storing capacitor and a bit line.
CONSTITUTION: A low resistance Si layer 32 to be a bit line is deposited on an insulating substrate 31 to form an Si layer 33 to be a channel region on the central part of the surface of the layer 32. Next the layer 33 is encircled by an insulating film 34 wherein a word line 35 is buried while a capacitor comprising a metal layer 36 to be one side electrode and a metal oxide film 37 with high permittivity is formed to coat the oxide film 37 with a metal grounding electrode 38. Through these procedures, a memory with integration much higher than a plane memory may be produced by means of vertically supplying the substrate 31 with electric charge being stored as memory.
KETSUSAKO MITSUNORI
MIYAO MASANOBU
| JPS55132063A | 1980-10-14 | |||
| JPS57103350A | 1982-06-26 | |||
| JPS5195742A | 1976-08-21 |