Title:
SEMICONDUCTOR MEMORY MANUFACTURING METHOD AND FAIL BIT MAP VERIFICATION METHOD
Document Type and Number:
Japanese Patent JP2005243101
Kind Code:
A
Abstract:
To reduce manpower in sample creation for FBM verification, and to shorten a period of time required for the verification for the FBM.
A defective memory cell RM 1 is intentionally built into a redundant memory cell part 50. A memory cell M1 of a designated address in a regular memory cell part 40(regardless of being normal/defective) is replaced with the defective redundant memory cell RM 1. This enables the memory cell of the designated address in the regular memory cell part 40 to be intentionally made into the defective cell. This means a semiconductor memory sample for the FBM verification, in which the defective position is clear, can be created.
Inventors:
SAKURAI KEN
Application Number:
JP2004049114A
Publication Date:
September 08, 2005
Filing Date:
February 25, 2004
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/28; G11C29/00; G11C29/44; H01L21/66; (IPC1-7): G11C29/00; G01R31/28; H01L21/66
Attorney, Agent or Firm:
Shohei Oguri
Hironori Honda
Toshimitsu Ichikawa
Takeshi Takamatsu
Yuriko Hamada
Hironori Honda
Toshimitsu Ichikawa
Takeshi Takamatsu
Yuriko Hamada