To improve efficiency of redundancy processing by more speedily obtaining the line fail count after line determination than before, and to reduce a circuit scale on the side of a semiconductor memory test apparatus by dispensing with a line mask with respect to a semiconductor memory.
This apparatus is provided with a line fail counter which counts the numbers of fail cells detected from the semiconductor memory to be tested with respect to each of X-lines and Y-lines; and a line determination flag which is set when a fail cell positioned on a corresponding line can be repaired by assigning an X spare line and a Y spare line to the fail cells. On the basis of a set line determination flag, the fail cell positioned on the corresponding line is detected and the counted value of the line fail counter is subtracted and updated. On the basis of the subtracted and updated counted value of the line fail counter, the X spare line and the Y spare line are assigned in combination with each other to repair the unrepaired fail cells.
KIMURA TAKAHIRO