To provide a semiconductor storage device that can be operated at a low amplitude clock signal without making the circuitry complicated in order to turn on/off all the transistors (TRs) of the device driven by the low amplitude clock signal.

This invention provides the semiconductor storage device, which is provided with a 1st TR circuit including a 1st TR (P11), a 2nd TR (N72), and a 3rd TR (N73) connected between power supplies VDD and VSS, with a 2nd TR circuit including a 4th TR (P12), a 5th TR (N75) and a 6th TR (N76) connected between the power supplies VDD and VSS, and where an input signal (D) is supplied in common to the gates of the 1st and 2nd TRs, the clock signal (CLK or CLK') is fed to the gates of the 3rd and 6th TRs and a connecting point (X) of the 1st and 2nd TRs is connected in common to the gates of the 4th and 5th TRs.