To provide a D flip-flop circuit device receiving a clock signal and a data is asynchronously with each other that avoids the production of a meta stable state.

The D flip-flop circuit device including at least one D flip-flop that latches the data input signal in timing of the clock pulse and outputs the latched signal to a post-stage circuit as an output data signal, is provided with a synchronizing circuit that delays the output timing of the clock pulse supplied to the D flip-flop by a prescribed time so as to latch the data input signal in the timing so as not to take place meta stable.