Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4497645
Kind Code:
B2
Abstract:
A semiconductor memory device according to the present invention includes a memory core portion, a test mode control circuit for transmitting data output from the memory core portion to an internal node, and a data input/output control circuit for inputting/outputting in series a plurality of pieces of parallel data input/output to each internal node to a data node. The test mode control circuit transmits read data from the memory core portion as it is to the internal node in a normal reading operation, and compresses data output from the memory core portion on the basis of a prescribed unit and transmits the data to the internal node in a test mode. Therefore, the test data compressed for each prescribed unit can be input/output by using a smaller number of data nodes in the test mode than in the normal operation mode.
Inventors:
Masaki Tsukide
Application Number:
JP2000107921A
Publication Date:
July 07, 2010
Filing Date:
April 10, 2000
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C7/10; G01R31/28; G11C29/00; G11C29/34; G11C29/40
Domestic Patent References:
| JP2974219B2 | ||||
| JP10289600A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai