Title:
少なくとも2つの明確な抵抗状態を有するメモリ用の検知増幅器
Document Type and Number:
Japanese Patent JP4283769
Kind Code:
B2
Abstract:
In a memory, a sensing system detects bit states using one data and two reference inputs, to sense a difference in conductance of a selected memory bit cell and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell in the high conductance state and a memory cell in the low conductance state. The data input is coupled to the selected memory bit cell. The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages amplifies the sense amplifier output without injecting parasitic errors.
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Inventors:
Nahas, Joseph Jay.
Andre, Thomas W.
Garni, Bradley Jay.
Sabramanian, Chitra Kay.
Andre, Thomas W.
Garni, Bradley Jay.
Sabramanian, Chitra Kay.
Application Number:
JP2004517537A
Publication Date:
June 24, 2009
Filing Date:
May 01, 2003
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G11C11/15; G11C7/06; G11C7/14; G11C11/14
Domestic Patent References:
| JP2001184881A |
Foreign References:
| US5917753 | ||||
| US20020080644 | ||||
| US6269040 |
Attorney, Agent or Firm:
Mamoru Kuwagaki