To reduce the burdens of a circuit and to respond at high speed by transmitting the acknowledge of reception possibility in the case that a memory for reception is not free and transmitting the acknowledge of reception impossibility when a reception packet is a request packet to a prescribed register.

An inbound circuit 106 supplies reception packet data to both of an automatic response circuit 109 and a FIFO memory 104 for reception until confirming an address indicated by the destination offset area of the reception packet. In the case that a writable free area is not present in the FIFO memory 104 for the reception, that effect is reported to an acknowledge control circuit 107 by storage area information S104 and thus, the acknowledge of the reception possibility is transmitted through a link core 101. Then, when discrimination signals S106 from the inbound circuit 106 indicate that the reception packet is the request packet to the prescribed register, the acknowledge of the reception impossibility is transmitted.