To attain stable operation by controlling properly a delay time by detecting it when a delay time of a variable pulse delay circuit exceeds at least an input pulse at a high level period or a low level period.

A variable pulse delay circuit 1 delays an input pulse signal to obtain a delayed pulse signal add an EXOR 5a takes exclusive OR between the delayed pulse signal and the input pulse signal to obtain a clock SCK whose frequency is twice that of the input pulse signal. A DFF 5b detects detects it that a delay time of the variable pulse delay circuit 1 is an over-delay state where the delay time is larger than at least a low level period or a high level period of the input pulse signal and gives its detection output to an input of a charge pump circuit 3 via an OR circuit 5c. The charge pump circuit 3 and an error signal generating circuit 4 generate a signal Ix to control a delay time of the variable pulse delay circuit 1 according to the output of the OR circuit 5c.