To reduce the required memory capacity (buffer capacity).

The processor 1C is provided with a frame configuration buffer 101c that generates a frame signal 12c denoting a data quantity in the unit of bytes in response to a 1st data rate on a transmission line 3 on the basis of a received transmission data signal 11c, an error correction code insertion section 102c that inserts an error correction code Ec to the frame signal to generate an error correction code inserted signal 13c, modulation sections 103c, 104c that modulate the error correction code inserted signal 13C to output it to the transmission line 3, demodulation sections 107c, 108c that demodulate a received input data signal 19c received from the transmission line 3 to generate a demodulated signal 21c, an error correction section 109c that applies error correction processing to the demodulated signal 21c to generate an error correction frame signal 26c, and a frame separation buffer 110c that generates a reception output data signal 56c at a 2nd data rate on the basis of the error correction frame signal 26c.