Title:
SIMULATION METHOD AND MODEL FOR TROUBLE OF LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPS62290941
Kind Code:
A
Abstract:
A method for simulating an erroneously-delayed signal switching at the output of the logic circuit utilizing a modified simulation model which is inherently suited for the simulation of a stuck-open fault and which, in particular, comprises an output stage which takes the signal storage appearing given this fault into consideration is disclosed. The modification is comprised in that the storage behavior of the output stage is suppressed after one clock period.
Inventors:
JIIKUMAARU KETSUPE
Application Number:
JP14072687A
Publication Date:
December 17, 1987
Filing Date:
June 03, 1987
Export Citation:
Assignee:
SIEMENS AG
International Classes:
G06F11/25; G06F11/26; G06F17/50; G06F19/00; H03K19/00; H01L21/8234; H01L27/088; (IPC1-7): G06F11/26; G06F15/20; H01L27/08; H03K19/00
Attorney, Agent or Firm:
Tomimura Kiyoshi