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Patent Searching and Data


Title:
SIMULATION METHOD FOR RESIST PATTERN
Document Type and Number:
Japanese Patent JPH01209723
Kind Code:
A
Abstract:

PURPOSE: To make it possible to simulate the shape of resist effectively and adequately, by expressing the dissolving speed R of a resist film in a developer as a function of a normalized inhibitor concentration with a specified expression, and using said expression.

CONSTITUTION: In a program wherein simulation of a semiconductor manufacturing step, especially a lithography step, is performed, a dissolving speed R is expressed with a normalized inhibitor concentration of resist M. At this time, the following ways are carried out for expressing R(M) based on the actual measured values: (1) the pattern is divided into three regions in correspondence with the M-dependence of R; (2) the dissolving speed Rn(M) for each region is expressed by Rn(M)=exp(anM+bn), where an and bn are constants, and n=1, 2, 3; and (3) for the total M, R(M) is expressed by the expression R(M)=1/{(1/ R1)+(1/R2)}+R3. Thus, the dissolving speed characteristics of all high resolution resists which have been developed in recent years can be readily incorporated into the lithography simulators.


Inventors:
OFUJI TAKESHI
Application Number:
JP3590788A
Publication Date:
August 23, 1989
Filing Date:
February 17, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/30; G03F7/00; G03F7/30; G05B17/02; H01L21/027; (IPC1-7): G03C5/24; G03F7/00; G05B17/02; H01L21/30
Attorney, Agent or Firm:
Uchihara Shin