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Title:
SOLID ELECTROLYTIC CAPACITOR, SUBSTRATE WITH BUILT-IN SOLID ELECTROLYTIC CAPACITOR, AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP2009004417
Kind Code:
A
Abstract:

To enhance the functions of equipment using a high-speed IC or LSI, and to downsize the equipment by increasing larger capacity of a solid electrolytic capacitor and the flexibility of the wirings.

Disclosed is the solid electrolytic capacitor which has through wirings formed at at least one or more third insulating layer portions in floating-island shapes by providing at least one or more third insulating layers in floating-island shapes formed at portions of a dielectric film, a solid electrolytic layer formed on the dielectric film at outside parts of the third insulating layers, and a current collector layer as a cathode formed on the top surface of the solid electrolytic layer, forming a second through hole penetrating the third insulating layers, the dielectric film below them, and valve metal foil 1 as an anode in some third insulating layer portion where the first insulating layer is not formed, forming a third through hole penetrating the first insulating layer in a first through hole where the first insulating layer is formed, and providing a through hole electrode in the second and third through holes.


Inventors:
ISHITOMI HIROYUKI
ASAHI TOSHIYUKI
SUGAYA YASUHIRO
HIMORI GOJI
HASHIMOTO AKIRA
Application Number:
JP2007161074A
Publication Date:
January 08, 2009
Filing Date:
June 19, 2007
Export Citation:
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Assignee:
PANASONIC CORP
International Classes:
H01G9/04; H01G9/012; H01G9/048
Domestic Patent References:
JP2005294291A2005-10-20
JP2006165152A2006-06-22
Foreign References:
WO2007007830A12007-01-18
Attorney, Agent or Firm:
Fumio Iwahashi
Hiroki Naito
Daisuke Nagano