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Title:
SOLID-STATE IMAGE PICKUP DEVICE
Document Type and Number:
Japanese Patent JPH03258173
Kind Code:
A
Abstract:

PURPOSE: To reduce fixed pattern noise by setting a gate level of a JFET to a negative level at the start of a storage period after the end of a reset period.

CONSTITUTION: A gate level of a JFET2 is set to a negative level at the start of a storage period after the end of a reset period. An electron of an electron.electron-hole pair excited by an incident light for the storage period is absorbed by an n-channel layer and the electron hole is stored in a gate in the floating state. A channel conductance is modulated by a change in a gate level and the drain current is modulated and amplified. When a vertical selection MOSFET 4 of an n-th row is conductive by a vertical scanning pulse Yn, a drain current of the n-th row picture element charges a vertical signal line 13 of each column. A horizontal selection MOSFET 18 is conductive sequentially from a first column by horizontal scanning pulse x1, x2 during selection of the (n+1)th row of picture elements by a pulse Yn+1 and the stored charge in each column of vertical signal line 1 is sequentially outputted via a video signal line 19.


Inventors:
MORIMOTO TSUNEHIRO
Application Number:
JP5855490A
Publication Date:
November 18, 1991
Filing Date:
March 08, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/146; H04N5/335; H04N5/365; H04N5/369; H04N5/374; H04N5/3745; (IPC1-7): H01L27/146; H04N5/335
Attorney, Agent or Firm:
Uchihara Shin



 
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