To solve the problem of insufficiency of writing time of a video signal to a source line due to shortening of the pulse width of a sampling pulse with a high-frequency clock signal.

A sampling pulse (sam) is raised synchronously with fall of a start pulse (SP). When the start pulse (SP) is raised, the sampling pulse (sam) falls successively while being lagged from a clock signal (CK, CKB) by a half period per stage, synchronously with the rise of the clock signal (CK, CKB). As a result, a sampling pulse (sam) having a pulse width longer than one cycle of the clock signal (CK, CKB) is produced. A desired video signal (VIDEO) is written in a corresponding source line in a period Ta. Thereby, clock signal half cycle time is ensured for writing in a source line.