Title:
複数デジタル・ビットのための安定化回路
Document Type and Number:
Japanese Patent JP3706146
Kind Code:
B2
Abstract:
An integrated circuit memory system having memory cells capable of storing multiple bits per memory cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.
Inventors:
George J. Corsh
Khan, Sakawat M
Khan, Sakawat M
Application Number:
JP53914497A
Publication Date:
October 12, 2005
Filing Date:
April 28, 1997
Export Citation:
Assignee:
Agate Semiconductor Incorporated
International Classes:
G11C11/56; H03H1/00; G11C16/02; (IPC1-7): G11C16/02
Domestic Patent References:
| JP7037397A | ||||
| JP1134793A |
Foreign References:
| US5479170 | ||||
| WO1996024138A1 |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa