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Patent Searching and Data


Title:
STATIC RAM CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS58220296
Kind Code:
A
Abstract:

PURPOSE: To reduce the test time of an RAM part for a static RAM containing a data writing/reading circuit, by using a test circuit which controls both writing and reading directions of data.

CONSTITUTION: It is supposed that either one of points (a)W(d) is open or short as a factor for a defect of an RAM. For instance, "0" is supplied to a DATAIN to check the open at the point (a) or (b) and the short at the point (d). Then a ternary output buffer 8' and a ternary input buffer 7' are set in a writing state and a non-writing state respectively. Thus the data is written to the RAM through the buffer 8'. If no defect exists, a point Q, i.e., a real output of the RAM is set at "0" and then read out to a DATAOUT. Thus the data written into the RAM is instantaneously read and checked, and therefore the test time is reduced.


Inventors:
NAKAMURA TAKAYOSHI
KOSAKA HIDETOSHI
Application Number:
JP10261782A
Publication Date:
December 21, 1983
Filing Date:
June 15, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/417; G11C29/00; G11C29/08; G11C29/12; (IPC1-7): G11C11/34; G11C29/00
Attorney, Agent or Firm:
Uchihara Shin