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Title:
SUBSTRATE FOR SEMICONDUCTOR PACKAGE, AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2002313996
Kind Code:
A
Abstract:

To provide a highly reliable semiconductor package where a load is not applied to a semiconductor chip at stacking by reducing the dispersion of the height of a bump.

A copper-laminated plate 15, where the thickness of a copper foil 11 is selected optimally in consideration of the height requested for a bump 6, is prepared, and the copper foil 11 of this copper-laminated plate 15 is selectively removed thereby forming the bump 6. The bump 6 where height accuracy on approximately the same level as the copper foil 11 is obtained, and a highly reliable semiconductor package where a load is not applied to a semiconductor part 12 can be provided, and also the margin to be added at decision of the height of the bump can be reduced, and the package can be made thin as a whole.


Inventors:
TAKEYAMA YASUHIRO
Application Number:
JP2001120254A
Publication Date:
October 25, 2002
Filing Date:
April 18, 2001
Export Citation:
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Assignee:
TOSHIBA CHEM CORP
International Classes:
H01L23/12; H01L21/60; H01L25/065; H01L25/07; H01L25/18; (IPC1-7): H01L23/12; H01L21/60; H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Suyama Saichi