To provide a successive approximation A-D conversion circuit that improves digital data transfer speed after the A-D conversion is carried out while controlling the number of external wiring.

The successive approximation A-D conversion circuit 11 includes an output digital data generating portion 6 disposed on a digital chip Dchip. The output digital data generating portion 6 receives comparison results V2 from a comparator 2 formed on an analog chip Achip. The output digital data generating portion 6 carries out successive approximation as internal processing based on the comparison results V2. The results A-D conversion that are data stored after the successive approximation is carried out are then outputted to the other digital circuits formed on the identical digital chip Dchip as parallel output digital data PDout. Further, the output digital data generating portion 6 includes a timing signal generating function that outputs a timing signal Stm for giving instructions to a DA data setting portion 4 as to whether or not A-D conversion should be started.