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Title:
SUPER COLOR-TYPE MICROPROCESSOR
Document Type and Number:
Japanese Patent JP3654137
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a processor architecture of high ability which is suitable to be realized by using a microprocessor, by simultaneously executing instructions fetched from instruction storage.
SOLUTION: An instruction fetch unit(IFU) 102 and an instruction execution unit(IEU) 104 are function elements being the center of an architecture 100. Instruction sets formed of four instructions are simultaneously fetched by IFU 102 from an instruction cache 132 in a cache control unit(CCU) 106 via an instruction bus 114. An instruction stream fetched by IFU 102 is transferred to IEU 104 via an instruction stream bus 124. IEU 104 stores data through a bi-directional data bus 130 with a data cache 134 installed in CCU 106 and takes out the data. IEU 104 is provided with a function managing the parallel execution of plural instructions.


Inventors:
Nguyen, Retron
Lenz, Derek Jay.
Miyama, Yoshiyuki
Gargu, Sanjib
Hagiwara, Yasuaki
One, Johannes
Lau, Terri
Trang, Kwan H.
Application Number:
JP2000145123A
Publication Date:
June 02, 2005
Filing Date:
July 07, 1992
Export Citation:
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Assignee:
Seiko Epson Corporation
International Classes:
G06F9/32; G06F9/30; G06F9/34; G06F9/38; G06F9/42; (IPC1-7): G06F9/38
Domestic Patent References:
JP2022736A
JP64036336A
Other References:
William M.Johnson,Super-Scalar Processor Design,Ph.D. dissertation, Technical Report No.CSL-TR-89-383,米国,Stanford University,1989年 6月,pp.1-134
久我守弘、外4名,SIMP(単一命令流/多重命令パイプライン)方式に基づく『新風』プロセッサの低レベル並列処理アルゴリズム,情報処理学会論文誌,日本,1989年12月15日,Vol.30, No.12,pp.1603 - 1611
Mike Johnson,Superscalar Microprocessor Design,米国,Prentice Hall,1991年,pp.1-272
Attorney, Agent or Firm:
Meisei International Patent Office
Hirukawa Masanobu
Ryukichi Abe
Norihiko Uchida
Hideo Sugai
Kenji Aoki
Hiroshi Nagisawa
Akira Yonezawa