SUPER SCALAR-TYPE MICRO PROCESSOR

Japanese Patent JP3654138

B2

PROBLEM TO BE SOLVED: To provide a super scalar-type processor architecture of the RISC base of high performance, which is suitably realized by a micro processor, by installing the data storage of a different set for temporarily storing register data in a register file.
SOLUTION: A fetch unit IFU 102 fetching instructions where one instruction contains register reference from a memory in a program order which is previously decided and a register file containing a previously decided register and a temporary register storing an execution result out of the order are provided. An execution unit IEU 104 connected to the fetch unit IFU 102 simultaneously executes at least two instructions, executes one of instructions out of the previously decided program order and stores the execution result in the temporary register based on register reference. Furthermore, a data bus system routing data among the register, the temporary register and plural function units is installed.

Nguyen, Retron
Lenz, Derek Jay.
Miyama, Yoshiyuki
Gargu, Sanjib
Hagiwara, Yasuaki
One, Johannes
Lau, Terri
Trang, Kwan H.

JP2000145125A

June 02, 2005

July 07, 1992

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Seiko Epson Corporation

G06F9/32; G06F9/30; G06F9/34; G06F9/38; G06F9/42; (IPC1-7): G06F9/38; G06F9/34

JP2022736A
JP64036336A

William M.Johnson,Super-Scalar Processor Design,Ph.D. dissertation, Technical Report No.CSL-TR-89-383,米国,Stanford University,1989年 6月,pp.1-134
久我守弘、外4名,SIMP(単一命令流/多重命令パイプライン)方式に基づく『新風』プロセッサの低レベル並列処理アルゴリズム,情報処理学会論文誌,日本,1989年12月15日,Vol.30, No.12,pp.1603 - 1611
Mike Johnson,Superscalar Microprocessor Design,米国,Prentice Hall,1991年,pp.1-272

Meisei International Patent Office
Hirukawa Masanobu
Ryukichi Abe
Norihiko Uchida
Hideo Sugai
Kenji Aoki
Hiroshi Nagisawa
Akira Yonezawa

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