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Patent Searching and Data


Title:
SV SIGNAL PROPAGATION CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH03270522
Kind Code:
A
Abstract:

PURPOSE: To make the processing of an SV(supervisor) signal proper and to prevent production of malfunction by checking an address of the SV signal at an SV execution section of a controlled object repeater and stopping the output of the SV signal when the address is coincident with its own address.

CONSTITUTION: An address 2 entering a shift register 31 is compared with an address of an controlled object repeater by an address comparator 37. In the case of dissidence, a transmission direction switch 36 is used to send an SV instruction signal in a similar format to its own line. When the address is coincident with its own address, the address comparator 37 activates an attribute decoding section 38. The decoding section 38 decodes an attribute 4 in the shift register 31 and opens a gate 39 when it is an instruction to send a data part 3 form the shift register 31 to a decoder 29. Then the instruction is decoded by the decoder 29 to allow an SV operating section 30 to execute the instruction. The processing of the SV instruction is terminated up to the section 30 and no loopback of the SV instruction signal takes place.


Inventors:
INADA HITOSHI
TANIGAWA KAZUYUKI
MAKI TAKANORI
Application Number:
JP7105890A
Publication Date:
December 02, 1991
Filing Date:
March 20, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B10/07; H04B3/36; H04B10/035; H04B10/077; H04B10/54; H04B17/40; (IPC1-7): H04B3/36; H04B10/08; H04B17/02
Attorney, Agent or Firm:
Minoru Aoyagi