To provide the SYNC word detection circuit by using a few logic gates so as to detect a SYNC word easily.

A high level (that is, '1') bit signal of a SYNC word is given to an AND gate AND1 of a 1st logic gate 2, and a low level (that is, '0') bit signal of the SYNC word is given to an OR gate OR2 of a 2nd logic gate 3. The AND hate AND2 and the OR gate OR2 output respectively a high level flag signal FG2 and a low level flag signal FG2 to the control section 4 only when they receive the SYNC word going to be detected, and the control section 4 discriminates it that the received data are the SYNC word based on flag signals FG1, FG2.