To prevent adverse effect due to deviation in the synchronization caused when a plurality of asynchronous input serial digital audio data are selected by a switch.

A receiver 10 recovers a clock signal from input data AES, a synchronization detection circuit 12 detects a synchronization code from output data from the receiver to generate an input enable INEN. An input AND gate 16 receives the INEN and the recovered clock and gives the data from the receiver to an FIFO 14 in response to the output. The synchronization detection circuit receives a common system synchronizing signal to generate an output enable OUTEN. An output AND gate 18 provides an output of synchronizing data from a plurality of the FIFO in response to the OUTEN and a common output clock.