Title:
半導体装置を用いるシステム
Document Type and Number:
Japanese Patent JP7257772
Kind Code:
B2
Abstract:
A semiconductor device capable of suppressing performance degradation and systems using the same are provided. The semiconductor device includes a plurality of processors CPU1 and CPU2, a scheduling device 10 (ID1) connected to the processors CPU1 and CPU2 for controlling the processors CPU1 and CPU2 to execute a plurality of tasks in real time, memories 17 and 18 accessed by the processors CPU1 and CPU2 to store data by executing the tasks, and access monitor circuits 15 for monitoring accesses to the memories by the processors CPU1 and CPU2. When an access to the memory is detected by the access monitor circuit 15, the data stored in the memory 18 is transferred based on the destination information of the data stored in the memory 18.
Inventors:
Taro Sasaki
Application Number:
JP2018205515A
Publication Date:
April 14, 2023
Filing Date:
October 31, 2018
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G06F9/54; G06F9/50; G06F13/28; G06F15/173
Domestic Patent References:
| JP5046576A | ||||
| JP6028303A | ||||
| JP2000293480A | ||||
| JP62267833A | ||||
| JP11045232A | ||||
| JP2011516950A | ||||
| JP2008097084A | ||||
| JP2000122880A |
Attorney, Agent or Firm:
Patent Attorney Tsutsui International Patent Office
Previous Patent: How to press the sealing material
Next Patent: Wound type non-aqueous electrolyte secondary battery
Next Patent: Wound type non-aqueous electrolyte secondary battery