Title:
LOGIC CIRCUIT SIMULATION RESULT DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP3146254
Kind Code:
B2
Abstract:
PURPOSE: To unnecessitate to purchase special simulators and to eliminate manual computation and troublesome operations by displaying the superposition of waveform of the change delay of each signal change point based on the simulation result using the minimum, standard, and maximum delay.
CONSTITUTION: A logic circuit is inputted on a computer from a logic circuit input means 201. Then a test pattern input means 22 prepares test patterns at its input. A computer executes three types of simulations such as the minimum delay, standard delay, and maximum delay to provide respective results. The timing inspection is performed by waveform-displaying the result. Based on the simulation result of the minimum delay, standard delay, and maximum delay, the phase of the waveform is checked, thereby displaying the delay of change point position in each delay at the normal phase section.
More Like This:
| JPH0520383 | LOGIC VERIFICATION DEVICE |
| WO/1992/020026 | KNOWLEDGE BASED RESOURCE MANAGEMENT |
| JPH03116277 | SIMULATION SYSTEM AND SIMULATION METHOD |
Inventors:
Toshio Yamamoto
Application Number:
JP6815392A
Publication Date:
March 12, 2001
Filing Date:
March 26, 1992
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F11/25; G01R31/28; G06F11/26; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP5143670A | ||||
| JP4172563A | ||||
| JP3184177A | ||||
| JP3138766A | ||||
| JP2105232A | ||||
| JP6398042A | ||||
| JP61219878A |
Attorney, Agent or Firm:
Masatoshi Isomura