PURPOSE: To enable setting of a test mode by the least necessary number of pins corresponding to the number of logic function blocks by providing a test mode setting circuit having a circuit construction which is controlled by a test signal, a load signal and a test data signal.

CONSTITUTION: When a test signal 9 is in an ordinary mode, a test mode setting circuit 13 is reset and does not accept inputs of a load signal 10 and a test data signal 11. When the signal 9 is in a test mode, in contrast, the signal 11 is read in the circuit 13 by the signal 10 and test mode signals 12a to 12h corresponding to the signal 11 are outputted sequentially. At the time T, for instance, only the signal 12f outputs an effective value ad a logic function block connected thereto is activated and subjected to a function test. On the occasion, a plurality of test mode setting signals can be made effective at the time T by the signal 11. The number of test mode setting signals of the circuit 13 can be increased and decreased in accordance with the number of logic function blocks which are tested.