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Patent Searching and Data


Title:
TEST VECTOR GENERATING METHOD
Document Type and Number:
Japanese Patent JPH08114657
Kind Code:
A
Abstract:

PURPOSE: To make it possible to effectively test an ultra-LSI (VLSI) circuit by taking out a failed function circuit, and combining it with a trouble-free function circuit to form a compound function circuit, etc.

CONSTITUTION: A failed function circuit is pulled out, and combined with a trouble-free function circuit to form a compound function circuit. The function of energy of the compound function circuit is pulled out as a collection of secondary and tertiary terms. Then, a transitive closure(TC) of restriction which can be represented as a secondary-term relation, is determined to verify inconsistency, identification, fixation, and exclusion. The TC of a digital circuit is calculated from a directionally oriented graph and an implication graph. A directed edge in third graph is represented by an equation, and represents a controlling action of a true state of a signal x relating to a failed state of a signal y. A new secondary term is added to the directed edge to form a new implication graph, and a list of literals is pulled out. Then, test vectors in relation to failures are pulled out from the list of literals.


Inventors:
SURIMATSUTO CHIYAKURADAARU
BISHIYUWANI AGURAWARU
Application Number:
JP20174992A
Publication Date:
May 07, 1996
Filing Date:
June 18, 1992
Export Citation:
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Assignee:
NEC CORP
BISHIYUWANI AGURAWARU
International Classes:
G01R31/3183; G06F11/22; G06F17/50; (IPC1-7): G01R31/3183; G06F11/22
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)