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Patent Searching and Data


Title:
TESTING DEVICE AND METHOD
Document Type and Number:
Japanese Patent JP2008275337
Kind Code:
A
Abstract:

To provide a testing device and a test method capable of measuring efficiently an input/output characteristic of a test object circuit equipped with a plurality of input terminals, synchronously with a clock.

A clock CLK is applied to flip-flops 5a, 5b as resistor circuits into which output data from a test circuit 4 are input together with a circuit block 3, and an output signal changing synchronously with the clock CLK is inputted into a buffer circuit 6 as a test object circuit. The test circuit 4 is set in a test operation mode including a plurality of modes by switching internal multiplexers 11a, 11b corresponding to a test signal TST[a:b] used as a mode switching signal. An output value of the test circuit 4 is changed by a plurality of combinations by switching setting to each of the plurality of modes, and thereby the input/output characteristics during an AC test time of the buffer circuit 6 can be measured efficiently.


Inventors:
NINNA YASUYUKI
Application Number:
JP2007115924A
Publication Date:
November 13, 2008
Filing Date:
April 25, 2007
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA INFORMATION SYS JAPAN
International Classes:
G01R31/28; G01R31/3185; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Susumu Ito