Title:
【発明の名称】自動適応型等化器
Document Type and Number:
Japanese Patent JP3068440
Kind Code:
B2
Abstract:
PURPOSE: To attain proper distortion equalization, to make the circuit small and to reduce power consumption by detecting a timewise fluctuation rate of an interference control signal to control a time constant for averaging processing of the interference control signal. CONSTITUTION: A control signal generator 13 in a control signal generating circuit 12 calculates correlation between quadrant discrimination signals Dp, Dq and error signals Ep, Eq to be received to generate an interference control signal 101 to apply waveform equalization to multi-path fading generated in a transmission line and gives it to an averaging circuit 14. The circuit 14 averages the signal 101 to generate an equalization circuit control signal 102 to allow a distortion equalization circuit 11 to execute distortion equalization. In this case, the signal 102 being an output waveform of the circuit 14 is changed by the signal 101 corresponding to fading in the transmission line. Furthermore, the circuit 14 changes a time constant by a time constant control signal 103 received from a fluctuation detection circuit 15, then the circuit traces with fluctuation in multi-path fading and keeps an error rate characteristic in an optimum state.
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Inventors:
Masaaki Michida
Application Number:
JP15984995A
Publication Date:
July 24, 2000
Filing Date:
June 02, 1995
Export Citation:
Assignee:
NEC
International Classes:
H03H21/00; H04B3/06; H04B7/005; H04L27/01; (IPC1-7): H04B7/005; H03H21/00; H04B3/06; H04L27/01
Domestic Patent References:
| JP4208707A | ||||
| JP56122219A | ||||
| JP6416128A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)