Title:
【発明の名称】積分レベル調整装置
Document Type and Number:
Japanese Patent JP2665335
Kind Code:
B2
Abstract:
PURPOSE:To substantially expand the dynamic range of an integration means by controlling the ratio of intermission of signal passing in a gate means so as to control the substantial integration time of an input signal thereby adjusting the integration level. CONSTITUTION:The titled integration level adjuster is constituted by a signal controller outputting an exposure correction signal EX and a chopping signal CH, analog switches 6, 7 and a NAND gate 10. When exposure correction is applied, the exposure correction signal EH goes to H and the analog switches 6, 7 are subject to on/off control in response to the duty ratio of the output signal being the inversion of the level of the chopping signal CH from the system controller via the NAND gate 10. Thus, even when the level of the input signal from an image pickup element is large, the integrated output value as the result of integration for one field period by field integration storage circuits 16-18 does not exceed the dynamic range of the circuits 16-18.
Inventors:
Hideaki Yoshida
Application Number:
JP12786387A
Publication Date:
October 22, 1997
Filing Date:
May 25, 1987
Export Citation:
Assignee:
Olympus Optical Co., Ltd.
International Classes:
G01R15/09; G01J1/44; G01R15/08; G02B7/28; G03B7/08; G05B11/40; H03K4/02; H04N5/232; (IPC1-7): H03K4/02; G02B7/28; G03B7/08; H04N5/232
Domestic Patent References:
| JPS5786766A | ||||
| JP61179889B |
Attorney, Agent or Firm:
Susumu Ito