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Patent Searching and Data


Title:
PHASED ARRAY RECEIVER
Document Type and Number:
Japanese Patent JPS5928682
Kind Code:
A
Abstract:

PURPOSE: To obtain a device which can deal with linear scanning or sector scanning or intermediate scanning thereof and has working efficiency of delay lines by drawing out independently signals from the respective blocks constituted of the delay lines and cross point switches CPSW and connecting the respective delay lines in series.

CONSTITUTION: The echo signal from an oscillator A1 passes an amplifier U1 and is introduced from the switches indicated by the black spots of a CPSW 30 into a delay line 10. This signal passes further the route of an amplifier C1→ the contact V of SW1→ a delay line 11→ an amplifier G2→ the contact V of SW2→ a delay line 12→ an amplifier G3 and arrives at the Z contact of SW3. The echo signal from an oscillator A2 passes the lines 11 and 12 and arrives at the Z contact of the SW3. The echo signal from an oscillator A3 is introduced into the line 12. The echo signal from an oscillator A4 runs an amplifier U12, and arrives at the Z contact of the SW3 through the line 12 from the switches indicating CPSW32 with balck spots. The echo signals from the oscillators A1W A4 respectively delayed in time and are finally drawn out in the same phase from the Z contact of the SW3.


Inventors:
SHIMAZAKI TOORU
Application Number:
JP13895782A
Publication Date:
February 15, 1984
Filing Date:
August 10, 1982
Export Citation:
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Assignee:
YOKOGAWA HOKUSHIN ELECTRIC
International Classes:
A61B8/00; A61B8/14; G01N29/24; G01S7/52; G01S7/523; (IPC1-7): A61B10/00; G01N29/04
Attorney, Agent or Firm:
Shinsuke Ozawa