Title:
【発明の名称】出力バッファ回路
Document Type and Number:
Japanese Patent JP2655096
Kind Code:
B2
Abstract:
In an output buffer circuit so configured that a capacitor connected to a gate of an output driving MOS transistor and including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor, so as to realize a slow rising or falling time, there is additionally provided a threshold voltage charging circuit for rapidly charging the capacitor to a threshold voltage level of the output driving MOS transistor when the output driving MOS transistor is to be turned on. With this arrangement, the propagation delay time of an output voltage can be minimized.
Inventors:
OONISHI YASUHIRO
Application Number:
JP23515194A
Publication Date:
September 17, 1997
Filing Date:
September 29, 1994
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03K4/00; H03K17/04; H03K17/16; H03K17/687; H03K19/003; H03K19/017; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/04; H03K17/16; H03K19/003
Domestic Patent References:
| JP6422109A | ||||
| JP2309809A | ||||
| JP282713A | ||||
| JP537321A | ||||
| JP2285711A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)