Title:
【発明の名称】PLL回路
Document Type and Number:
Japanese Patent JP3327249
Kind Code:
B2
Abstract:
To provide a high speed digital PLL circuit which is easily manufactured by IC process. The phase of data signal is locked with a first clock of which frequency is the half of the data signal. Further, a second clock of which phase is shifted by pi/2 compared with the first clock is used for determining phase delay or phase advance of the data signal compared with the first clock. VCO outputs the first clock and the second clock. The phase comparator for inputting the data signal, the first and second clock, outputs a first data sampled at rise up of the first clock, a second data sampled at fall down of the first clock, a first indication signal indicating the phase delay, and a second indication signal indicating the phase advance. The filter for inputting the first and second indication signal outputs a control voltage for VCO.
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Inventors:
Masaaki Hayata
Application Number:
JP13003499A
Publication Date:
September 24, 2002
Filing Date:
May 11, 1999
Export Citation:
Assignee:
NEC
International Classes:
H03D13/00; H03K5/26; H03L7/08; H03L7/089; H03L7/091; H04L7/033; (IPC1-7): H03L7/089; H03K5/26; H03L7/08; H04L7/033
Domestic Patent References:
| JP11112335A | ||||
| JP10126400A |
Attorney, Agent or Firm:
Johei Yamashita