Title:
【発明の名称】直並列変換器
Document Type and Number:
Japanese Patent JP2689379
Kind Code:
B2
Abstract:
A serial bit stream (10) and a clock signal (14) at a frequency equal to the bit rate divided by an integer n are passed in opposite directions via respective delay lines (31-37, 41-47) to respectively the data (D) and clock inputs (C) of n flip-flops (21-28), which thereby each latch a respective one of n bits of the bit stream during n/2 bit periods. During the next n/2 bit periods the outputs (Q) of the flip-flops (21-28) are stable, and the n bits are latched in a parallel data latch (12). The delay lines comprise transmission lines terminated with their effective characteristic impedances (38, 48). The converter is particularly useful for bit rates greater than 1Gb/s.
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Inventors:
Stephen Chillers Carlton
Application Number:
JP24328786A
Publication Date:
December 10, 1997
Filing Date:
October 15, 1986
Export Citation:
Assignee:
North-Telecom Limited
International Classes:
H03M9/00; H04L25/40; H04L13/10; (IPC1-7): H03M9/00; H04L25/40
Domestic Patent References:
| JP54150940A |
Attorney, Agent or Firm:
Heiyoshi Odashima