PURPOSE: To provide a command holding circuit which is capable of holding a command by a right phase when noise exists, regarding the command holding circuit designating the operation mode of a device.

CONSTITUTION: This circuit has a counter circuit 1 starting the count by a discrimination pulse showing the leading bit of a serial command, a holding timing generation circuit 2 detecting the matching of the phase of the count value which is outputted by the counter circuit 1 and is equal to the bit number (n) of the serial command and the phase of the discrimination pulse showing the final bit of the serial command and generating a holding signal, a serial/ parallel conversion circuit 4 performing a parallel conversion of the serial command and a holding flip-flop 3 holding the output of the serial/parallel conversion circuit 4 by the output of the holding timing generation circuit 2.