Title:
【発明の名称】計数回路のテスト方法
Document Type and Number:
Japanese Patent JPH0758321
Kind Code:
B2
Abstract:
PURPOSE:To shorten the generation period of a carry signal from the least significant digit bit of cascaded counting circuits by cascading the small counting circuits and inputting counting input signals of the respective small counting circuits to a flip-flop properly. CONSTITUTION:The counting circuit is e quipped with, for example, four stages of cascaded counting means Q01-Q04. A counting input signal is inputted to the 1st-stage counting means Q01 and the output C0 of the 4th-stage counting means Q04 is connected to one input of a 1st AND gate G11. The counting input signal is connected to one input of a 2nd AND gate G12. The outputs of AND gates G11 and G12 are connected to the input of an OR gate G13. Further, the test flip-flop FF 100 is set with a test signal 1 and reset with a test signal 2. When the FF 100 is set, a positive logic output TQ and the inverse of TQ of a negative logic output are '1' and '0' respectively and the counting input signal of the least significant bit is connected to the inputs of the respective counting circuits in common. Consequently, the carry signal period is shortened and a test time is also shortened.
Inventors:
Hidetoshi Kosaka
Application Number:
JP27610087A
Publication Date:
June 21, 1995
Filing Date:
October 31, 1987
Export Citation:
Assignee:
NEC
International Classes:
G01R31/28; G01R31/317; H03K21/00; G01R31/3185; H03K23/00; (IPC1-7): G01R31/317
Domestic Patent References:
| JP6089127A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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