PURPOSE: To obtain a voltage converting circuit which transmits an input signal at a high speed and has low power consumption, by inputting the input signal and a signal, which is obtained by adding a certain voltage to the input signal, to a CMOS circuit through voltage limiting FETs respectively.

CONSTITUTION: When an input Vi is lower than a voltage V1-VTN1 (VTN1 is the threshold value of a FETT1), the FETT1 is turned on and an FETT2 is turned off, and therefore, the potential at an output point E is V4. When the input Vi becomes higher, both FETs are turned off, and the potential at the output point E is held in V4. When the input V1 is higher furthermore to exceed a voltage VTP2+VF+V2-V3, the FETT2 is turned on, and therefore the potential at a point D becomes V3-VF+Vi, and the potential at the output point E becomes 0. On the contrary, when the input Vi is lower, the potential at the output point E is held 0 until the input Vi is lower than V1-VTN1, and therefore, hysteresis is given, and rise and fall of the output are made sharp to transmit the signal at a high speed.