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Title:
COMPLEMENTARY MOS LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JPS5916425
Kind Code:
A
Abstract:

PURPOSE: To attain multi-stage cascade connection, by taking a logical section with series connection of plural N-channel depletion MOSFETs and inserting a P-channel MOSFET between one end of the logical section and an output terminal for decreasing number of elements.

CONSTITUTION: The MOSFETs 51, 52, 53 connected in series in the logical section 50 are all turned on when three logical signals A, B, C are at a high level. A connecting point 57 is set to a level higher than the potential of a power supply. Since the MOSFET55 turns on, an output terminal 54 is set to a high level. When at least one of the logical input signals A, B, C is at a low level, the FET is turned off. The potential at the connecting point 57 is fixed to an absolute value of the threshold voltage of the N-channel depletion MOSFET in this case. The FET55 is turned off. The output terminal 54 is kept to a low level with the presence of a resistor 56. The logical signal of the logical input signals A, B, C is obtained at the output terminal 54.


Inventors:
KOIKE HIDEJI
Application Number:
JP12610582A
Publication Date:
January 27, 1984
Filing Date:
July 20, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03K19/0948; (IPC1-7): H03K19/094
Attorney, Agent or Firm:
Takehiko Suzue



 
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